Samsung's Memory Stack Goes Vertical: What zHBM, zNAND-O, and V10 BV-NAND Actually Mean

The moment that defines where AI memory is heading isn't a shipping product — it's a concept model that nobody can buy yet. That's fine, and it's worth saying upfront. This week, Samsung presented its vision for next-generation memory and storage at the Future of Memory and Storage (FMS) 2026 conference, introducing zHBM, zNAND-O, and BV-NAND — three technologies aimed at very different applications that share one common ingredient: they all rely on wafer bonding. Understanding what each one actually is — and which ones you should take seriously right now — requires separating the roadmap from the product catalog.

The Common Thread: Wafer Bonding

Before unpacking each technology individually, the wafer bonding thread matters. The reason Samsung can claim radical density and efficiency improvements across all three products is that wafer bonding gives manufacturers a path toward higher density without simply extending already extreme vertical strings. Separating the CMOS and memory wafers allows each section to be manufactured and optimized independently, though additional bonding steps increase process complexity. That last part — process complexity — is exactly why these announcements range from "in customers' hands" to "still a physical concept model."

zHBM: The Geometry Shift That Matters Most

zHBM presents a new memory architecture that vertically stacks HBM directly above AI accelerators, moving beyond conventional designs in which HBM is positioned alongside the processor. That's not a subtle tweak. In conventional high-performance computing and AI server designs, HBM packages sit alongside the processor on a silicon interposer. While fast, this horizontal layout still forces data to travel across a significant physical distance between the RAM and the GPU or accelerator.

The specs Samsung is projecting are genuinely eye-opening: a next-generation interface system incorporating zHBM is expected to deliver significantly higher performance than HBM5, while wafer bonding technology enables substantially greater memory density, improved energy efficiency, and reduced thermal resistance compared to HBM5.

Those numbers need context, and a few outlets provided it honestly. The performance figures deserve a caveat: HBM5 is not a shipping product with a published specification, so these figures compare one concept against another concept. HBM4 still isn't deployed commercially yet, so these are quite the claims versus a far-future technology.

The thermal resistance claim is actually the most structurally interesting part of the zHBM announcement, because it's the technical obstacle that explains why memory has sat beside processors for so long. Memory has stayed beside the processor rather than on top of it largely because of heat. A modern AI accelerator dissipates significant power, and DRAM retention degrades sharply with temperature. Putting a DRAM stack directly above the hottest die in the system means the memory has to survive that heat flux while the heat itself has to escape through the memory to reach the heatsink. Samsung's claim that wafer bonding reduces thermal resistance is either the breakthrough that makes vertical stacking viable, or the claim that will prove hardest to sustain at scale. Probably both, in sequence.

One additional detail worth flagging for engineers thinking about future SoC customization: zHBM supports customer-specific designs, enabling customized IP to be integrated into the interlayer between the memory and AI accelerator to expand memory capacity and enhance accelerator performance. That's a structural shift toward chiplet-style co-design between memory and compute — meaningful if it ships.

zNAND-O: Not the Same Target at All

Unlike zHBM, which is built for AI accelerators, zNAND-O is designed for on-device AI — artificial intelligence tasks processed locally on a device rather than in a remote data center. zNAND-O is a next-generation high-performance NAND solution built on Samsung's V-NAND technology. By combining high space efficiency, improved I/O performance and low latency, it is optimized for edge AI environments supporting real-time, data-intensive AI applications.

The chip combines conventional NAND's layered structure with a bonding technique that packages multiple semiconductor chips together, boosting storage density while reducing physical size. Think phones, edge inference nodes, and local AI applications — not hyperscale training clusters. That's a different market, a different supply chain, and a different deployment timeline, and conflating it with zHBM undersells how distinct these two bets actually are.

Samsung did not disclose capacity, endurance, access latency, or commercialization timing for zNAND-O. So: directional, not deployable.

V10 BV-NAND: The One That's Actually Shipping (Soon)

This is where the announcement gets concrete. Samsung's V10 BV-NAND uses a new Bonding V-NAND architecture with advanced layering, built using wafer bonding technology to stack memory cells. The announcement comes over a decade after Samsung introduced the industry's first V-NAND. V10 BV-NAND increases memory density significantly over the previous generation, while also improving read, write, and I/O performance.

This density jump represents a legitimate generational leap for enterprise NAND. V10 BV-NAND leverages wafer bonding and 3-Stack technology to achieve this ultra-high stacking architecture. For AI infrastructure operators, denser NAND means more model checkpoints and training datasets per rack, faster I/O on the storage tier, and potentially fewer SSDs needed to hit a given capacity target.

Alongside V10, Samsung also reinforced that its nearer-term HBM roadmap is already in motion. Samsung was the first to begin shipping HBM4E samples to global customers in recent months. That's the real state of the art in Samsung's shipping product line — not zHBM.

Reading the Room on the Competitive Backdrop

These announcements align with a broader trend in the AI market. While demand for AI memory was initially driven primarily by the training of large language models, the need for fast storage for inference is now growing as well. As a result, demand is increasing for memory with higher capacity, greater bandwidth, and lower power consumption — and innovation is shifting not only toward faster AI processors but also toward the underlying memory architecture.

None of the flagship concepts are in production yet, but the direction is clear: Samsung wants to reclaim the AI memory lead it lost to SK Hynix. That competitive framing is worth holding onto. The three-technology FMS showcase is not a coincidence of timing — it's a deliberate demonstration of breadth across DRAM, NAND, and enterprise storage simultaneously. As the only integrated device manufacturer spanning memory, foundry, and advanced packaging, Samsung is positioning itself to move these concepts from lab preview to production faster than competitors relying on outside partners for each piece of the stack.

Whether that vertical integration advantage materializes in zHBM before SK Hynix or another player lands competing architecture is the real question this show opened without answering.

---